跪求 verilog 怎么写一个串口发送一帧的程序
最新回答
青春喂了作业
2024-04-16 00:08:10
module send(in_num,start,clk,out_num,finish);
//实现以start高电平为开始信号的FPGA到PC的数据传输，波特率9600（每发送一字节进行同步）
input [7:0] in_num;
input start; //控制数据发送开始
input clk;
output out_num;
output finish;
reg out_num;
reg finish;
reg [3:0] state;
reg [20:0] temp;reg [8:0] temp1;reg [8:0] temp2;reg [8:0] temp3;reg [8:0] temp4;reg [8:0] temp5;reg [8:0] temp6;reg [8:0] temp7;reg [8:0] temp8;reg [8:0] temp9;
always @(posedge clk)
begin
case(state) //通过状态跳转实现协议中的电平信号传输，并行变串行
0:
begin
out_num<=1;
finish<=0;
temp<=0;
if(start==1) //考虑到模块最终在系统中所处位置，采用电平触发方式，只需调整控制信号长度即可
state<=1;
else
state<=0;
end
1:
begin
out_num<=0; //起始位
temp1<=temp1+1;
if(temp1==15) //clk信号每16个周期发送一位数据，temp变量用于计数，下同
begin
state<=2;
temp1<=0;
end
else
state<=1;
end
2:
begin
out_num<=in_num[0]; //并行变串行，最低位，下同
temp2<=temp2+1;
if(temp2==15)
begin
state<=3;
temp2<=0;
end
else
state<=2;
end
3:
begin
out_num<=in_num[1];
temp3<=temp3+1;
if(temp3==15)
begin
state<=4;
temp3<=0;
end
else
state<=3;
end
4:
begin
out_num<=in_num[2];
temp4<=temp4+1;
if(temp4==15)
begin
state<=5;
temp4<=0;
end
else
state<=4;
end
5:
begin
out_num<=in_num[3];
temp5<=temp5+1;
if(temp5==15)
begin
state<=6;
temp5<=0;
end
else
state<=5;
end
6:
begin
out_num<=in_num[4];
temp6<=temp6+1;
if(temp6==15)
begin
state<=7;
temp6<=0;
end
else
state<=6;
end
7:
begin
out_num<=in_num[5];
temp7<=temp7+1;
if(temp7==15)
begin
state<=8;
temp7<=0;
end
else
state<=7;
end
8:
begin
out_num<=in_num[6];
temp8<=temp8+1;
if(temp8==15)
begin
state<=9;
temp8<=0;
end
else
state<=8;
end
9:
begin
out_num<=in_num[7];
temp9<=temp9+1;
if(temp9==15)
begin
state<=10;
temp9<=0;
end
else
state<=9;
end
10:
begin
finish<=1;
temp<=temp+1;
out_num<=1;
if(temp>=50) //控制状态时间长度，便于接口衔接
state<=0;
else
state<=10;
end
endcase
end
endmodule
孤凫
2024-04-16 00:03:31
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